Welcome to the Companion Site for Computer Organization and Design: The Hardware/Software Interface ARM Edition
This site contains supplemental materials and other resources to accompany Computer Organization and Design: The Hardware/Software Interface ARM Edition. Below are descriptions of the content available on this site. To access the content, please click the tabs in the navigation bar to the left.
- Supplements for the Fifth (MIPS) Edition. If you are using the Fifth (MIPS) Edition, you can access the supplements for that title by following these links.
- Historical Perspectives with References. For each chapter in the text, there is a section devoted to a historical perspective, together with references.
- Advanced Content. These are full-length sections covering advanced topics. These sections are introduced in each chapter of the text and can be found here.
- References Appendices. These appendices are available in PDF and include:
- Appendix B: Graphics and Computing GPUs
- Appendix C: Mapping Control to Hardware
- Appendix D: A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
- Glossary. Terms that are introduced and defined in the text are collected in this searchable PDF document.
- Index. A complete index of the text and online content, in a searchable PDF format.
- Further Reading. References are organized by the chapter they support in this PDF document.
- ARM Reference Data (Green Card). The ARM Reference Data sheet, aka, "Green Card", identical to that which appears in the printed text, is available as a PDF.
- Errata Sheet. Errata for the current edition is available here.
- VHDL/Verilog Tutorials. Tutorials for both VHDL and Verilog are available here.
- Software. Links to a free Community Edition of ARM DS-5 professional software suite which contains an ARMv8-A (64-bit) architecture simulator are available here.
- Test Case Module (Section 5.12). Link to a Test Case module that will be useful to check the code in these figures featured in Section 5.12. This SystemVerilog code can be used to create a cache and cache controller in an FPGA.
- Link to the instructor-only materials. The instructor-only materials, including solutions to all exercises, figures from the text, and lecture slides are available to instructors who register at our textbook Web site.